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publication number s29al016m_00 revision a amendment 5 issue date august 18, 2004 datasheet s29al016m 16 megabit (2 m x 8-bit/1 m x 16-bit) 3.0 volt-only boot sector flash memory featuring mirrorbit tm te c h n o l o g y data sheet distinctive characteristics architectural advantages ? single power supply operation ? 3 v for read, erase, and program operations ? manufactured on 0.23 m mirrorbit tm process technology ? secsi tm (secured silicon) sector region ? 128-word/256-byte sector for permanent, secure identification through an 8-word/16-byte random electronic serial number, accessible through a command sequence ? may be programmed and locked at the factory or by the customer ? flexible sector architecture ? one 16 kbyte, two 8 kbyte, one 32 kbyte, and thirty- one 64 kbyte sectors (byte mode) ? one 8 kword, two 4 kword, one 16 kword, and thirty- one 32 kword sectors (word mode) ? compatibility with jedec standards ? provides pinout and software compatibility for single- power supply flash, and superior inadvertent write protection ? top or bottom boot block configurations available ? 100,000 erase cycle typical per sector ? 20-year typical data retention performance characteristics ? high performance ? 90 ns access time ? 0.7 s typical sector erase time ? low power consumption (typical values at 5 mhz) ? 400 na standby mode current ? 15 ma read current ? 40 ma program/erase current ? 400 na automatic sleep mode current ? package options ? 48-ball fine-pitch bga ? 64-ball fortified bga ?48-pin tsop software features ? program suspend & resume: read other sectors before programming operation is completed ? erase suspend & resume: read/program other sectors before an erase operation is completed ? data# polling & toggle bits provide status ? unlock bypass program command reduces overall multiple-word programming time ? cfi (common flash interface) compliant: allows host system to identify and accommodate multiple flash devices hardware features ? sector protection: hardware-level method of preventing write operations within a sector ? temporary sector unprotect: v id -level method of changing code in locked sectors ? hardware reset input (reset#) resets device ? ready/busy# output (ry/by#) indicates program or erase cycle completion
2s29al016m s29al016m_00a5 august 18, 2004 general description the s29al016m is a 16 mbit, 3.0 volt-only flash memory organized as 2,097,152 bytes or 1,048,576 words. the device is offered in a 48-ball fine-pitch bga, 64- ball fortified bga, and 48-pin tsop packages. the word-wide data (x16) appears on dq15?dq0; the byte-wide (x8) data appears on dq7?dq0. the device re - quires only a single 3.0 volt power supply for both read and write functions, designed to be programmed in-system with the standard system 3.0 volt v cc sup - ply. the device can also be programmed in standard eprom programmers. the device offers access times of 90 and 100 ns. to eliminate bus contention the device has separate chip enable (ce#), write enable (we#) and output enable (oe#) controls. the device is entirely command set compatible with the jedec single-power- supply flash standard . commands are written to the device using standard microprocessor write timing. write cycles also internally latch addresses and data needed for the programming and erase operations. the sector erase architecture allows memory sectors to be erased and repro - grammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. device programming and erasure are initiated through command sequences. once a program or erase operation has begun, the host system need only poll the dq7 (data# polling) or dq6 (toggle) status bits or monitor the ready/ busy# (ry/by#) output to determine whether the operation is complete. to facilitate programming, an unlock bypass mode reduces command sequence overhead by requiring only two write cycles to program data instead of four. hardware data protection measures include a low v cc detector that automati - cally inhibits write operations during power transitions. the hardware sector protection feature disables both program and erase operations in any combina - tion of sectors of memory. this can be achieved in-system or via programming equipment. the erase suspend/erase resume feature allows the host system to pause an erase operation in a given sector to read or program any other sector and then complete the erase operation. the program suspend/program resume fea - ture enables the host system to pause a program operation in a given sector to read any other sector and then complete the program operation. the hardware reset# pin terminates any operation in progress and resets the device, after which it is then ready for a new operation. the reset# pin may be tied to the system reset circuitry. a system reset would thus also reset the de - vice, enabling the host system to read boot-up firmware from the flash memory device. the device reduces power consumption in the standby mode when it detects specific voltage levels on ce# and reset#, or when addresses have been stable for a specified period of time. the secsi ? (secured silicon) sector provides a 128-word/256-byte area for code or data that can be permanently protected. once this sector is protected, no further changes within the sector can occur. mirrorbit flash technology combines years of flash memory manufacturing expe - rience to produce the highest levels of quality, reliability and cost effectiveness. the device electrically erases all bits within a sector simultaneously via hot-hole assisted erase. the data is programmed using hot electron injection.
august 18, 2004 s29al016m_00a5 s29al016m 3 table of contents s29al016m general description . . . . . . . . . . . . . . . . . . . . . . . . 2 product selector guide . . . . . . . . . . . . . . . . . . . . . 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 connection diagrams . . . . . . . . . . . . . . . . . . . . . . 5 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 8 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ordering information . . . . . . . . . . . . . . . . . . . . . . . 9 device bus operations . . . . . . . . . . . . . . . . . . . . . . 10 table 1. s29al016m device bus operations ......................... 10 word/byte configuration ................................................................................ 10 requirements for reading array data ......................................................... 10 writing commands/command sequences .................................................. 11 program and erase operation status ............................................................ 11 standby mode ........................................................................................................ 11 automatic sleep mode ...................................................................................... 12 reset#: hardware reset pin ......................................................................... 12 output disable mode ........................................................................................ 12 table 2. sector address tables (model 01, top boot device) ... 13 table 3. sector address tables (model 02, bottom boot device) ..................................................................... 14 autoselect mode ................................................................................................. 14 table 4. autoselect codes (high voltage method) .................. 15 sector protection/unprotection .....................................................................15 temporary sector unprotect ......................................................................... 16 figure 1. temporary sector unprotect operation.................... 16 figure 2. in-system single high voltage sector protect/ unprotect algorithms .......................................................... 17 secsi (secured silicon) sector flash memory region .............................. 18 table 5. secsi sector addressing ......................................... 18 customer lockable: secsi sector not programmed or protected at the factory ........................................................................................................ 18 figure 3. secsi sector protect verify..................................... 19 common flash memory interface (cfi) ...................................................... 19 table 6. cfi query identification string ................................ 20 table 7. system interface string ......................................... 21 table 8. device geometry definition .................................... 21 table 9. primary vendor-specific extended query ................. 22 hardware data protection ............................................................................. 22 low v cc write inhibit ................................................................................. 22 write pulse ?glitch? protection ............................................................... 22 logical inhibit ...................................................................................................23 power-up write inhibit ................................................................................23 command definitions . . . . . . . . . . . . . . . . . . . . . .23 reading array data ............................................................................................23 reset command ..................................................................................................23 autoselect command sequence ................................................................... 24 word/byte program command sequence ................................................ 24 unlock bypass command sequence .........................................................25 figure 4. program operation................................................ 26 chip erase command sequence ................................................................... 26 sector erase command sequence .................................................................27 erase suspend/erase resume commands ...................................................27 figure 5. erase operation ................................................... 29 program suspend/program resume command sequence .................... 29 figure 6. program suspend/program resume........................ 30 command definitions tables .......................................................................... 31 table 10. command definitions (x16 mode, byte# = v ih ) ...... 31 table 11. command definitions (x8 mode, byte# = v il ) ........ 32 write operation status . . . . . . . . . . . . . . . . . . . . . 33 dq7: data# polling .............................................................................................33 figure 7. data# polling algorithm ........................................ 34 ry/by#: ready/busy# ....................................................................................... 34 dq6: toggle bit i ............................................................................................... 35 dq2: toggle bit ii .............................................................................................. 35 reading toggle bits dq6/dq2 ..................................................................... 36 figure 8. toggle bit algorithm ............................................. 37 dq5: exceeded timing limits ........................................................................ 37 dq3: sector erase timer ................................................................................ 38 table 12. write operation status ......................................... 38 absolute maximum ratings . . . . . . . . . . . . . . . . . 39 figure 9. maximum negative overshoot waveform ................ 39 figure 10. maximum positive overshoot waveform ................ 39 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . 39 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . .40 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 11. test setup......................................................... 41 table 13. test specifications ............................................... 41 figure 12. input waveforms and measurement levels ............ 41 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . .42 read operations ................................................................................................. 42 figure 13. read operations timings ..................................... 42 hardware reset (reset#) .............................................................................. 43 figure 14. reset# timings................................................. 43 erase/program operations .............................................................................. 44 figure 15. program operation timings ................................. 45 figure 16. chip/sector erase operation timings .................... 46 figure 17. data# polling timings (during embedded algorithms) ........................................... 47 figure 18. toggle bit timings (during embedded algorithms) ........................................... 47 figure 19. dq2 vs. dq6 for erase and erase suspend operations .................................................. 48 figure 20. temporary sector unprotect/timing diagram......... 48 figure 21. sector protect/unprotect timing diagram .............. 49 figure 22. alternate ce# controlled write operation timings .. 51 erase and programming performance . . . . . . . . . 52 tsop pin and bga package capacitance . . . . . 52 physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . 53 ts 048?48-pin standard tsop .................................................................... 53 tsr048?48-pin reverse tsop .................................................................... 54 fba048?48-ball fine-pitch ball grid array (bga) 6 x 8 mm package .............................................................................................. 55 laa064?64-ball fortified ball grid array (bga) 13 x 11 mm package ............................................................................................. 56 revision summary . . . . . . . . . . . . . . . . . . . . . . . . 57
4s29al016m s29al016m_00a5 august 18, 2004 product selector guide notes: 1. see ?ac characteristics? for full specifications. 2. contact sales office or representative for availability and ordering information. block diagram family part number s29al016m speed option full voltage range: v cc = 2.7?3.6 v 90 100 max access time (ns) 90 100 max ce# access time (ns) 90 100 max oe# access time (ns) 25 25 input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss we# byte# ce# oe# stb stb dq15?dq0 (a-1) sector switches ry/by# reset# data latch y-gating cell matrix address latch a19?a0
august 18, 2004 s29al016m_00a5 s29al016m 5 connection diagrams a1 a15 a18 a14 a13 a12 a11 a10 a9 a8 a19 nc we# reset# nc nc ry/by# a17 a7 a6 a5 a4 a3 a2 1 16 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 9 10 11 12 13 14 15 a16 dq2 byte# v ss dq15/a-1 dq7 dq14 dq6 dq13 dq9 dq1 dq8 dq0 oe# v ss ce# a0 dq5 dq12 dq4 v cc dq11 dq3 dq10 48 33 47 46 45 44 43 42 41 40 39 38 37 36 35 34 25 32 31 30 29 28 27 26 standard tsop
6s29al016m s29al016m_00a5 august 18, 2004 connection diagrams a1 b1 c1 d1 e1 f1 g1 h1 a2 b2 c2 d2 e2 f2 g2 h2 a3 b3 c3 d3 e3 f3 g3 h3 a4 b4 c4 d4 e4 f4 g4 h4 a5 b5 c5 d5 e5 f5 g5 h5 a6 b6 c6 d6 e6 f6 g6 h6 dq15/a-1 v ss byte# a16 a15 a14 a12 a13 dq13 dq6 dq14 dq7 a11 a10 a8 a9 v cc dq4 dq12 dq5 a19 nc reset# we# dq11 dq3 dq10 dq2 nc a18 nc ry/by# dq9 dq1 dq8 dq0 a5 a6 a17 a7 oe# v ss ce# a0 a1 a2 a4 a3 fine-pitch bga top view, balls facing down
august 18, 2004 s29al016m_00a5 s29al016m 7 connection diagrams special package handling instructions special handling is required for flash memory products in molded packages (tsop, bga, ssop, pdip, plcc). the package and/or data integrity may be compromised if the package body is exposed to temperatures above 150 c for prolonged periods of time. b3 c3 d3 e3 f3 g3 h3 b4 c4 d4 e4 f4 g4 h4 b5 c5 d5 e5 f5 g5 h5 b6 c6 d6 e6 f6 g6 h6 b7 c7 d7 e7 f7 g7 h7 b8 c8 d8 e8 f8 g8 h8 nc nc nc v ss nc nc nc v ss dq15/a-1 byte# a16 a15 a14 a12 dq6 dq13 dq14 dq7 a11 a10 a8 dq4 v cc dq12 dq5 a19 nc reset# dq3 dq11 dq10 dq2 nc a18 nc dq1 dq9 dq8 dq0 a5 a6 a17 a3 a4 a5 a6 a7 a8 nc a13 a9 we# ry/by# a7 b2 c2 d2 e2 f2 g2 h2 v ss oe# ce# a0 a1 a2 a4 a2 a3 b1 c1 d1 e1 f1 g1 h1 nc nc nc nc nc nc nc a1 nc 64-ball fortified bga top view, balls facing down
8s29al016m s29al016m_00a5 august 18, 2004 pin configuration a19?a0 = 20 addresses dq14?dq0 = 15 data inputs/outputs dq15/a-1 = dq15 (data input/output, word mode), a-1 (lsb address input, byte mode) byte# = selects 8-bit or 16-bit mode ce# = chip enable oe# = output enable we# = write enable reset# = hardware reset pin ry/by# = ready/busy output v cc = 3.0 volt-only single power supply (see product selector guide for speed options and voltage supply tolerances) v ss = device ground nc = pin not connected internally logic symbol 20 16 or 8 dq15?dq0 (a-1) a19?a0 ce# oe# we# reset# byte# ry/by#
august 18, 2004 s29al016m_00a5 s29al016m 9 ordering information standard products spansion standard products are available in several packages and operating ranges. the order number (valid combinatio n) is formed by a combination of the elements below. notes: 1. type 0 is standard. specify others as required: tsops can be packed in types 0 and 3; bgas can be packed in types 0, 2, or 3. 2. tsop package marking omits packing type designator from ordering part number. 3. bga package marking omits leading ?s29? and packing type designator from ordering part number. valid combinations valid combinations list configurations plan ned to be supported in volume for this device. consult your local sales office to confirm availability of specific valid com - binations and to check on newly released combinations. s29al016m 90 t a i 01 2 packing type 0=tray 2 = 7? tape & reel 3 = 13? tape & reel additional ordering options 01 = x8/x16, v cc = 2.7?3.6 v, top boot sector device r1 = x8/x16, v cc = 3.0?3.6 v, top boot sector device 02 = x8/x16, v cc = 2.7?3.6 v, bottom boot sector device r2 = x8/x16, v cc = 3.0?3.6 v, bottom boot sector device temperature range i = industrial (?40 c to +85 c) package material set a=standard f=pb-free package type t = thin small outline package (tsop) standard pinout b = fine-pitch ball grid array (bga) f = fortified ball grid array (bga) speed option see product selector guide and valid combinations device number/description s29al016m 16 megabit (2m x 8-bit/1m x 16-bit) mirrorbit tm flash memory 3.0 volt-only read, program, and erase s29al016m valid combinations package description device number speed option package, material, & temperature range model number packing type s29al016m 90, 100 tai, tfi 01, r1, 02, r2 0, 2, 3 (note 1) ts048 (note 2) tsop bai, bfi fba048 (note 3) fine-pitch bga fai, ffi laa064 (note 3) fortified bga
10 s29al016m s29al016m_00a5 august 18, 2004 device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addressable memory location. the register is com - posed of latches that store the commands, along with the address and data information needed to execute the command. the contents of the register serve as inputs to the internal state machin e. the state machine outputs dictate the function of the device. table 1 lists the device bus operations, the inputs and con - trol levels they require, and the resu lting output. the following subsections describe each of these operations in further detail. ta b l e 1 . s29al016m device bus operations legend: l = logic low = v il , h = logic high = v ih , v id = 12.0 0.5 v, x = don?t care, a in = address in, d in = data in, d out = data out notes: 1. addresses are a19:a0 in word mode (byte# = v ih ), a19:a-1 in byte mode (byte# = v il ). 2. the sector protect and sector unprotect functions may also be implemented via programming equipment. see the ?sector protection/unprotection? section. word/byte configuration the byte# pin controls whether the device data i/o pins dq15?dq0 operate in the byte or word configuration. if the byte# pin is set at logic ?1?, the device is in word configuration, dq15?dq0 are active and controlled by ce# and oe#. if the byte# pin is set at logic ?0?, the device is in byte configuration, and only data i/o pins dq0?dq7 are active and co ntrolled by ce# and oe#. the data i/ o pins dq8?dq14 are tri-stated, and the dq15 pin is used as an input for the lsb (a-1) address function. requirements for reading array data to read array data from the outputs, the system must drive the ce# and oe# pins to v il . ce# is the power control and selects the device. oe# is the output control and gates array data to the output pins. we# should remain at v ih . the byte# pin determines whether the device outputs array data in words or bytes. operation ce# oe# we# reset# addresses (note 1) dq0? dq7 dq8?dq15 byte# = v ih byte# = v il read l l h h a in d out d out dq8?dq14 = high-z, dq15 = a-1 write l h l h a in d in d in standby v cc 0.3 v x x v cc 0.3 v x high-z high-z high-z output disable l h h h x high-z high-z high-z reset x x x l x high-z high-z high-z sector protect (note 2) l h l v id sector address, a6 = l, a1 = h, a0 = l d in x x sector unprotect (note 2) l h l v id sector address, a6 = h, a1 = h, a0 = l d in x x temporary sector unprotect x x x v id a in d in d in high-z
august 18, 2004 s29al016m_00a5 s29al016m 11 the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the mem - ory content occurs during the power transition. no command is necessary in this mode to obtain array data. standa rd microprocessor read cycles that as - sert valid addresses on the device address inputs produce valid data on the device data outputs. the device remains enabled for read access until the com - mand register contents are altered. see ?reading array data? for more information. refer to the ac read operations table for timing specifications and to figure 13 for the timing diagram. i cc1 in the dc characteristics table represents the active current specification for reading array data. writing commands/command sequences to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive we# and ce# to v il , and oe# to v ih . for program operations, the byte# pin determines whether the device accepts program data in bytes or words. refer to ?word configuration? for more information. the device features an unlock bypass mode to facilitate faster programming. once the device enters the unlock bypass mode, only two write cycles are re - quired to program a word or byte, instead of four. the ?word program command sequence? section has details on programming data to the device using both standard and unlock bypass command sequences. an erase operation can erase one sector, multiple sectors, or the entire device. tables 2 and 3 indicate the address space that each sector occupies. a ?sector address? consists of the address bits required to uniquely select a sector. the ?command definitions? section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. after the system writes the autoselect command sequence, the device enters the autoselect mode. the system can then re ad autoselect codes from the internal register (which is separate from the memory array) on dq7?dq0. standard read cycle timings apply in this mode. refer to the ?autoselect mode? and ?autoselect command sequence? sections for more information. i cc2 in the dc characteristics table represents the active current specification for the write mode. the ?ac characteristics? section contains timing specification ta - bles and timing diagrams for write operations. program and erase operation status during an erase or program operation, the system may check the status of the operation by reading the status bits on dq7?dq0. standard read cycle timings and i cc read specifications apply. refer to ?write operation status? for more in - formation, and to ?ac characteristics? for timing diagrams. standby mode when the system is not reading or writing to the device, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the oe# input.
12 s29al016m s29al016m_00a5 august 18, 2004 the device enters the cmos standby mode when the ce# and reset# pins are both held at v cc 0.3 v. (note that this is a more restricted voltage range than v ih .) if ce# and reset# are held at v ih , but not within v cc 0.3 v, the device will be in the standby mode, but the standby current will be greater. the device requires standard access time (t ce ) for read access when the device is in either of these standby modes, before it is ready to read data. if the device is deselected during erasure or programming, the device draws ac - tive current until the operation is completed. in the dc characteristics table, i cc3 and i cc4 represents the standby current specification. automatic sleep mode the automatic sleep mode minimizes flash device energy consumption. the device automatically enables this mode when addresses remain stable for t acc + 30 ns. the automatic sleep mode is independent of the ce#, we#, and oe# control signals. standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. i cc4 in the dc characteristics table represents the automatic sleep mode current specification. reset#: hardware reset pin the reset# pin provides a hardware method of resetting the device to reading array data. when the system drives the reset# pin to v il for at least a period of t rp , the device immediately terminates any operation in progress, tristates all data output pins, and ignores all read/write attempts for the duration of the re - set# pulse. the device also resets the internal state machine to reading array data. the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. current is reduced for the duration of the reset# pulse. when reset# is held at v ss 0.3 v, the device draws cmos standby current (i cc4 ). if reset# is held at v il but not within v ss 0.3 v, the standby current will be greater. the reset# pin may be tied to the system reset circuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firm - ware from the flash memory. if reset# is asserted during a program or erase operation, the ry/by# pin re - mains a ?0? (busy) until the internal reset operation is complete, which requires a time of t ready (during embedded algorithms). the system can thus monitor ry/by# to determine whether the reset operation is complete. if reset# is as - serted when a program or erase operation is not executing (ry/by# pin is ?1?), the reset operation is completed within a time of t ready (not during embedded algorithms). the system can read data t rh after the reset# pin returns to v ih . refer to the ac characteristics tables for reset# parameters and to figure 14 for the timing diagram. output disable mode when the oe# input is at v ih , output from the device is disabled. the output pins are placed in the high impedance state.
august 18, 2004 s29al016m_00a5 s29al016m 13 ta b l e 2 . sector address tables (model 01, top boot device) note: address range is a19:a-1 in byte mode and a19:a0 in word mode. see ?word/byte configuration? section. sector a19 a18 a17 a16 a15 a14 a13 a12 sector size (kbytes/ kwords) address range (in hexadecimal) byte mode (x8) word mode (x16) sa0 0 0 0 0 0 x x x 64/32 000000?00ffff 000000?007fff sa1 0 0 0 0 1 x x x 64/32 010000?01ffff 008000?00ffff sa2 0 0 0 1 0 x x x 64/32 020000?02ffff 010000?017fff sa3 0 0 0 1 1 x x x 64/32 030000?03ffff 018000?01ffff sa4 0 0 1 0 0 x x x 64/32 040000?04ffff 020000?027fff sa5 0 0 1 0 1 x x x 64/32 050000?05ffff 028000?02ffff sa6 0 0 1 1 0 x x x 64/32 060000?06ffff 030000?037fff sa7 0 0 1 1 1 x x x 64/32 070000?07ffff 038000?03ffff sa8 0 1 0 0 0 x x x 64/32 080000?08ffff 040000?047fff sa9 0 1 0 0 1 x x x 64/32 090000?09ffff 048000?04ffff sa10 0 1 0 1 0 x x x 64/32 0a0000?0affff 050000?057fff sa11 0 1 0 1 1 x x x 64/32 0b0000?0bffff 058000?05ffff sa12 0 1 1 0 0 x x x 64/32 0c0000?0cffff 060000?067fff sa13 0 1 1 0 1 x x x 64/32 0d0000?0dffff 068000?06ffff sa14 0 1 1 1 0 x x x 64/32 0e0000?0effff 070000?077fff sa15 0 1 1 1 1 x x x 64/32 0f0000?0fffff 078000?07ffff sa16 1 0 0 0 0 x x x 64/32 100000?10ffff 080000?087fff sa17 1 0 0 0 1 x x x 64/32 110000?11ffff 088000?08ffff sa18 1 0 0 1 0 x x x 64/32 120000?12ffff 090000?097fff sa19 1 0 0 1 1 x x x 64/32 130000?13ffff 098000?09ffff sa20 1 0 1 0 0 x x x 64/32 140000?14ffff 0a0000?0a7fff sa21 1 0 1 0 1 x x x 64/32 150000?15ffff 0a8000?affff sa22 1 0 1 1 0 x x x 64/32 160000?16ffff 0b0000?0b7fff sa23 1 0 1 1 1 x x x 64/32 170000?17ffff 0b8000?0bffff sa24 1 1 0 0 0 x x x 64/32 180000?18ffff 0c0000?0c7fff sa25 1 1 0 0 1 x x x 64/32 190000?19ffff 0c8000?0cffff sa26 1 1 0 1 0 x x x 64/32 1a0000?1affff 0d0000?0d7fff sa27 1 1 0 1 1 x x x 64/32 1b0000?1bffff 0d8000?0dffff sa28 1 1 1 0 0 x x x 64/32 1c0000?1cffff 0e0000?0e7fff sa29 1 1 1 0 1 x x x 64/32 1d0000?1dffff 0e8000?0effff sa30 1 1 1 1 0 x x x 64/32 1e0000?1effff 0f0000?0f7fff sa31 1 1 1 1 1 0 x x 32/16 1f0000?1f7fff 0f8000?0fbfff sa32 1 1 1 1 1 1 0 0 8/4 1f8000?1f9fff 0fc000?0fcfff sa33 1 1 1 1 1 1 0 1 8/4 1fa000?1fbfff 0fd000?0fdfff sa34 1 1 1 1 1 1 1 x 16/8 1fc000?1fffff 0fe000?0fffff
14 s29al016m s29al016m_00a5 august 18, 2004 ta b l e 3 . sector address tables (model 02, bottom boot device) note: address range is a19:a-1 in byte mode and a19:a0 in word mode. see the ?word/byte configuration? section. autoselect mode the autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on dq7?dq0. this mode is primarily intended for programming eq uipment to automatically match a device sector a19 a18 a17 a16 a15 a14 a13 a12 sector size (kbytes/ kwords) address range (in hexadecimal) byte mode (x8) word mode (x16) sa0 0 0 0 0 0 0 0 x 16/8 000000?003fff 000000?001fff sa1 0 0 0 0 0 0 1 0 8/4 004000?005fff 002000?002fff sa2 0 0 0 0 0 0 1 1 8/4 006000?007fff 003000?003fff sa3 0 0 0 0 0 1 x x 32/16 008000?00ffff 004000?007fff sa4 0 0 0 0 1 x x x 64/32 010000?01ffff 008000?00ffff sa5 0 0 0 1 0 x x x 64/32 020000?02ffff 010000?017fff sa6 0 0 0 1 1 x x x 64/32 030000?03ffff 018000?01ffff sa7 0 0 1 0 0 x x x 64/32 040000?04ffff 020000?027fff sa8 0 0 1 0 1 x x x 64/32 050000?05ffff 028000?02ffff sa9 0 0 1 1 0 x x x 64/32 060000?06ffff 030000?037fff sa10 0 0 1 1 1 x x x 64/32 070000?07ffff 038000?03ffff sa11 0 1 0 0 0 x x x 64/32 080000?08ffff 040000?047fff sa12 0 1 0 0 1 x x x 64/32 090000?09ffff 048000?04ffff sa13 0 1 0 1 0 x x x 64/32 0a0000?0affff 050000?057fff sa14 0 1 0 1 1 x x x 64/32 0b0000?0bffff 058000?05ffff sa15 0 1 1 0 0 x x x 64/32 0c0000?0cffff 060000?067fff sa16 0 1 1 0 1 x x x 64/32 0d0000?0dffff 068000?06ffff sa17 0 1 1 1 0 x x x 64/32 0e0000?0effff 070000?077fff sa18 0 1 1 1 1 x x x 64/32 0f0000?0fffff 078000?07ffff sa19 1 0 0 0 0 x x x 64/32 100000?10ffff 080000?087fff sa20 1 0 0 0 1 x x x 64/32 110000?11ffff 088000?08ffff sa21 1 0 0 1 0 x x x 64/32 120000?12ffff 090000?097fff sa22 1 0 0 1 1 x x x 64/32 130000?13ffff 098000?09ffff sa23 1 0 1 0 0 x x x 64/32 140000?14ffff 0a0000?0a7fff sa24 1 0 1 0 1 x x x 64/32 150000?15ffff 0a8000?0affff sa25 1 0 1 1 0 x x x 64/32 160000?16ffff 0b0000?0b7fff sa26 1 0 1 1 1 x x x 64/32 170000?17ffff 0b8000?0bffff sa27 1 1 0 0 0 x x x 64/32 180000?18ffff 0c0000?0c7fff sa28 1 1 0 0 1 x x x 64/32 190000?19ffff 0c8000?0cffff sa29 1 1 0 1 0 x x x 64/32 1a0000?1affff 0d0000?0d7fff sa30 1 1 0 1 1 x x x 64/32 1b0000?1bffff 0d8000?0dffff sa31 1 1 1 0 0 x x x 64/32 1c0000?1cffff 0e0000?0e7fff sa32 1 1 1 0 1 x x x 64/32 1d0000?1dffff 0e8000?0effff sa33 1 1 1 1 0 x x x 64/32 1e0000?1effff 0f0000?0f7fff sa34 1 1 1 1 1 x x x 64/32 1f0000?1fffff 0f8000?0fffff
august 18, 2004 s29al016m_00a5 s29al016m 15 to be programmed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode requires v id (11.5 v to 12.5 v) on address pin a9. address pins a6, a1, and a0 must be as shown in ta b l e 4 . in addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see tables 2 and 3 ). table 4 shows the remaining address bits that are don?t care. when all necessary bits have been set as required, the programming equipment may then read the cor - responding identifier code on dq7-dq0. to access the autoselect codes in-system, the host system can issue the autose - lect command via the command register, as shown in tables 10 ? 11 . this method does not require v id . see ?command definitions? for details on using the autose - lect mode. ta b l e 4 . autoselect codes (high voltage method) l = logic low = v il , h = logic high = v ih , sa = sector address, x = don?t care. note: the autoselect codes may also be accessed in-system via command sequences. see tables 10 ? 11 . sector protection/unprotection the hardware sector protection feature disables both program and erase opera - tions in any sector. the hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. the device is normally shipped with all sectors unprotected. however, the ex - pressflash? service offers the option of programming and protecting sectors at the factory prior to shipping the device. contact a sales office or representative for details. it is possible to determine whether a sector is protected or unprotected. see ?au - toselect mode? for details. description mode ce# oe# we# a19 to a12 a11 to a10 a9 a8 to a7 a6 a5 to a2 a1 a0 dq8 to dq15 dq7 to dq0 manufacturer id (spansion products) l l h x x v id x l x l l x 01h device id: s29al016m (model 01) (top boot block) word l l h x x v id x l x l h 22h c4h byte l l h x c4h device id: s29al016m (model 02) (bottom boot block) word l l h x x v id x l x l h 22h 49h byte l l h x 49h sector protection verification l l h sa x v id x l x h l x 01h (protected) x 00h (unprotected) secsi sector indicator bit (dq7) l l h x x v id x h x l h x 83 (factory locked 03h (not factory locked)
16 s29al016m s29al016m_00a5 august 18, 2004 sector protection and unprotection requires v id on the reset# pin only, and can be implemented either in-system or via programming equipment. figure 2 shows the algorithms and figure 23 shows the timing diagram. this method uses stan - dard microprocessor bus cycle timing. for sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. temporary sector unprotect this feature allows temporary unprotection of previously protected sectors to change data in-system. the sector unprotect mode is activated by setting the reset# pin to v id . during this mode, formerly protected sectors can be pro - grammed or erased by selecting the sector addresses. once v id is removed from the reset# pin, all the previously protected sectors are protected again. figure shows the algorithm, and figure 22 shows the timing diagrams, for this feature. notes: 1. all protected sectors unprotected. 2. all previously protected sectors are protected once again. figure 1. temporary sector unprotect operation start perform erase or program operations reset# = v ih temporary sector unprotect completed (note 2) reset# = v id (note 1)
august 18, 2004 s29al016m_00a5 s29al016m 17 figure 2. in-system single high voltage sector protect/unprotect algorithms sector protect: write 60h to sector address with a6 = 0, a1 = 1, a0 = 0 set up sector address wait 150 s verify sector protect: write 40h to sector address with a6 = 0, a1 = 1, a0 = 0 read from sector address with a6 = 0, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 ms first write cycle = 60h? data = 01h? remove v id from reset# write reset command sector protect complete yes yes no plscnt = 25? yes device failed increment plscnt temporary sector unprotect mode no sector unprotect: write 60h to sector address with a6 = 1, a1 = 1, a0 = 0 set up first sector address wait 15 ms verify sector unprotect: write 40h to sector address with a6 = 1, a1 = 1, a0 = 0 read from sector address with a6 = 1, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 ms data = 00h? last sector verified? remove v id from reset# write reset command sector unprotect complete yes no plscnt = 1000? yes device failed increment plscnt temporary sector unprotect mode no all sectors protected? yes protect all sectors: the indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address set up next sector address no yes no yes no no yes no in-system single high voltage sector protect algorithm in-system single high voltage sector unprotect algorithm first write cycle = 60h? protect another sector? reset plscnt = 1
18 s29al016m s29al016m_00a5 august 18, 2004 secsi (secured silicon) sector flash memory region the secsi (secured silicon) sector featur e provides a flash memory region that enables permanent part identification through an electronic serial number (esn). the secsi sector is 256 bytes in length, and uses a secsi sector indica - tor bit (dq7) to indicate whether or not the secsi sector is locked when shipped from the factory. this bit is permanently set at the factory and cannot be changed, which prevents cloning of a fa ctory locked part. this ensures the secu - rity of the esn once the product is shipped to the field. the device is offered with the secsi sector either customer lockable (standard shipping option) or factory locked (contact a sales office or representative for or - dering information). the customer-lockable version is shipped with the secsi sector unprotected, allowing customers to program the sector after receiving the device. the customer-lockable version also has the secsi sector indicator bit permanently set to a ?0.? the factory-locked version is always protected when shipped from the factory, and has the secsi (secured silicon) sector indi - cator bit permanently set to a ?1.? thus, the secsi sector indicator bit prevents customer-lockable devices from being used to replace devices that are factory locked. note that the acc function and unlock bypass modes are not available when the secsi sector is enabled. the secsi sector address space in this device is allocated as follows: ta b l e 5 . secsi sector addressing the system accesses the secsi sector through a command sequence (see ?en - ter secsi sector/exit secsi sector command sequence?). after the system has written the enter secsi sector command sequence, it may read the secsi sector by using the addresses given in ta b l e 5 . this mode of operation continues until the system issues the exit secsi sector command sequence, or until power is removed from the device. on power-up, or following a hardware reset, the de - vice reverts to sending commands to sector sa0. customer lockable: secsi sector not programmed or protected at the factory unless otherwise specified, the device is shipped such that the customer may program and protect the 256-byte secsi sector. the system may program the secsi sector using the write-buffer, accelerated and/or unlock bypass methods, in addition to the standard programming com - mand sequence. see command definitions. programming and protecting the secsi sector must be used with caution since, once protected, there is no procedure available for unprotecting the secsi sec - tor area and none of the bits in the secsi sector memory space can be modified in any way. the secsi sector area can be protected using one of the following procedures: ? write the three-cycle enter secsi sector region command sequence, and then follow the in-system sector protect algorithm as shown in figure 2, ex - secsi sector address range customer lockable esn factory locked expressflash factory locked x16 x8 0f8000h? 0f8007h 1f0000h- 1f000fh determined by customer esn esn or determined by customer 0f8008h? 0f807fh 1f0010h- 1f00ffh unavailable determined by customer
august 18, 2004 s29al016m_00a5 s29al016m 19 cept that reset# may be at either v ih or v id . this allows in-system protec - tion of the secsi sector without raising any device pin to a high voltage. note that this method is only applicable to the secsi sector. ? to verify the protect/unprotect status of the secsi sector, follow the algo - rithm shown in figure 3. once the secsi sector is programmed, locked and verified, the system must write the exit secsi sector region comm and sequence to return to reading and writing within the remainder of the array. factory locked: secsi sector programmed and protected at the factory in devices with an esn, the secsi sector is protected when the device is shipped from the factory. the secsi sector cannot be modified in any way. an esn fac - tory locked device has a 16-byte random esn at addresses given in ta b l e 5 . please contact your local sales office or representative for details on ordering esn factory locked devices. customers may opt to have their code programmed by the manufacturer through the expressflash service (express flash factory locked). the devices are then shipped from the factory with the secsi sector permanently locked. contact an sales office or representative for details on using the expressflash service. figure 3. secsi sector protect verify common flash memory interface (cfi) the common flash interface (cfi) specificati on outlines device and host system software interrogation handshake, which allows specific vendor-specified soft - ware algorithms to be used for entire families of devices. software support can then be device-independent, jedec id-independent, and forward- and back - write 60h to any address write 40h to secsi sector address with a6 = 0, a1 = 1, a0 = 0 start reset# = v ih or v id wait 1 ms read from secsi sector address with a6 = 0, a1 = 1, a0 = 0 if data = 00h, secsi sector is unprotected. if data = 01h, secsi sector is protected. remove v ih or v id from reset# write reset command secsi sector protect verify complete
20 s29al016m s29al016m_00a5 august 18, 2004 ward-compatible for the specified flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the system writes the cfi query command, 98h, to address 55h in word mode (or address aah in byte mode), any time the device is ready to read array da ta. the system can read cfi information at the addresses given in tables 6 ? 9 . in word mode, the upper address bits (a7? msb) must be all zeros. to terminate reading cfi data, the system must write the reset command. the system can also write the cfi query command when the device is in the au - toselect mode. the device enters the cfi query mode, and the system can read cfi data at the addresses given in tables 6 ? 9 . the system must write the reset command to return the device to the read/reset mode. for further information, please refer to the cfi specification and cfi publication 100, available online at http://www.amd.com/flash/cfi . alternatively, contact an sales office or representative for copies of these documents. table 6. cfi query identification string addresses (word mode) addresses (byte mode) data description 10h 11h 12h 20h 22h 24h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 26h 28h 0002h 0000h primary oem command set 15h 16h 2ah 2ch 0040h 0000h address for primary extended table 17h 18h 2eh 30h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 32h 34h 0000h 0000h address for alternate oem extended table (00h = none exists)
august 18, 2004 s29al016m_00a5 s29al016m 21 note: cfi data related to timeouts may differ from actual timeouts of the product. consult the ordering the erase and programming performance table for timeout guidelines. table 7. system interface string addresses (word mode) addresses (byte mode) data description 1bh 36h 0027h v cc min. (write/erase). d7?d4: volt, d3?d0: 100 millivolt 1ch 38h 0036h v cc max. (write/erase). d7?d4: volt, d3?d0: 100 millivolt 1dh 3ah 0000h v pp min. voltage (00h = no v pp pin present) 1eh 3ch 0000h v pp max. voltage (00h = no v pp pin present) 1fh 3eh 0007h typical timeout per single byte/word write 2 n s 20h 40h 0000h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 42h 000ah typical timeout per individual block erase 2 n ms 22h 44h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 46h 0001h reserved for future use 24h 48h 0000h max. timeout for buffer write 2 n times typical (00h = not supported) 25h 4ah 0004h max. timeout per individual block erase 2 n times typical 26h 4ch 0000h max. timeout for full chip erase 2 n times typical (00h = not supported) table 8. device geometry definition addresses (word mode) addresses (byte mode) data description 27h 4eh 0015h device size = 2 n byte 28h 29h 50h 52h 0002h 0000h flash device interface descriptio n (refer to cfi publication 100) 2ah 2bh 54h 56h 0000h 0000h max. number of byte in multi-byte write = 2 n (00h = not supported) 2ch 58h 0004h number of erase block regions within device 2dh 2eh 2fh 30h 5ah 5ch 5eh 60h 0000h 0000h 0040h 0000h erase block region 1 information (refer to the cfi specification or cfi publication 100) 31h 32h 33h 34h 62h 64h 66h 68h 0001h 0000h 0020h 0000h erase block region 2 information 35h 36h 37h 38h 6ah 6ch 6eh 70h 0000h 0000h 0080h 0000h erase block region 3 information 39h 3ah 3bh 3ch 72h 74h 76h 78h 001eh 0000h 0000h 0001h erase block region 4 information
22 s29al016m s29al016m_00a5 august 18, 2004 hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to tables 10 ? 11 for command definitions). in addition, the following hardware data protection mea - sures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than v lko , the device does not accept any write cycles. this pro - tects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to prevent unintentional writes when v cc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. table 9. primary vendor-specific extended query addresses (word mode) addresses (byte mode) data description 40h 41h 42h 80h 82h 84h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 86h 0031h major version number, ascii 44h 88h 0033h minor version number, ascii 45h 8ah 0008h address sensitive unlock (bit 1?0) 0b = required, 1b = not required process technology (bits 7?2) 0010b = 0.23 m mirrorbit 46h 8ch 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 8eh 0001h sector protect 0 = not supported, x = number of sectors in per group 48h 90h 0001h sector temporary unprotect 00 = not supported, 01 = supported 49h 92h 0004h sector protect/unprotect scheme 04 = standard mode 4ah 94h 0000h simultaneous operation 00 = not supported, 01 = supported 4bh 96h 0000h burst mode type 00 = not supported, 01 = supported 4ch 98h 0000h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page
august 18, 2004 s29al016m_00a5 s29al016m 23 logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = ce# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automatically reset to reading array data on power-up. command definitions writing specific address and data commands or sequences into the command register initiates device operations. tables 10 ? 11 define the valid register com - mand sequences. note that writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. a reset command is then required to set the device for the next operation. all addresses are latched on the falling edge of we# or ce#, whichever happens later. all data is latched on the rising edge of we# or ce#, whichever happens first. refer to the appropriate timing diagrams in the ?ac characteristics? section. reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is also ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the device enters the erase suspend mode. the system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see ?erase suspend/erase resume commands? for more in - formation on this mode. the system must issue the reset command to re-enable the device for reading array data if dq5 goes high, or wh ile in the autoselect mode. see the ?reset com - mand? section, next. see also ?requirements for reading array data? in the ?device bus operations? section for more information. the read operations table provides the read pa - rameters, and figure 13 shows the timing diagram. reset command writing the reset command to the device resets the device to reading array data. address bits are don?t care for this command. the reset command may be written between the sequence cycles in an erase command sequence before erasing begins. this resets the device to reading array data. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins. this resets the device to read - ing array data (also applies to programming in erase suspend mode). once programming begins, however, the device ignores reset commands until the op - eration is complete.
24 s29al016m s29al016m_00a5 august 18, 2004 the reset command may be written between the sequence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during erase suspend). if dq5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during erase suspend). autoselect command sequence the autoselect command sequence allows the host system to access the manu - facturer and devices codes, and determin e whether or not a sector is protected. ta b l e s 10 ? 11 show the address and data requirements. this method is an alter - native to that shown in table 4 , which is intended for prom programmers and requires v id on address bit a9. the autoselect command sequence is initiated by writing two unlock cycles, fol - lowed by the autoselect command. the device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. a read cycle at address xx00h retrieves the manufacturer code. a read cycle at address xx01h returns the device code. a read cycle containing a sector address (sa) and the address xx02h in word mode (or xx04h in byte mode) returns xx01h if that sector is protected, or 00h if it is unprotected. refer to tables 2 and 3 for valid sector addresses. the system must write the reset command to exit the autoselect mode and return to reading array data. word/byte program command sequence the system may program the device by word or byte, depending on the state of the byte# pin. programming is a four-bus-cycle operation. the program command sequence is initiated by writin g two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not re - quired to provide further controls or timings. the device automatically generates the program pulses and verifies the programmed cell margin. tables 10 ? 11 show the address and data requirements for the program command se - quence. note that the secsi sector, autoselect, and cfi functions are unavailable when a program operation is in progress. when the embedded program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. the system can deter - mine the status of the program operation by using dq7, dq6, or ry/by#. see ?write operation status? for information on these status bits. any commands written to the device during the embedded program algorithm are ignored. note that a hardware reset immediately terminates the program - ming operation. the program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. program - ming to the same address multiple times without intervening erases is limited. for such application requirements, please contact your local spansion represen - tative. any bit in a word or byte cannot be programmed from ?0? back to a ?1?. attempting to do so may halt the operation and set dq5 to ?1,? or cause the data# polling algorithm to indicate the operation was successful. however, a suc -
august 18, 2004 s29al016m_00a5 s29al016m 25 ceeding read will show that the data is still ?0?. only erase operations can convert a ?0? to a ?1?. unlock bypass command sequence the unlock bypass feature allows the system to program bytes or words to the device faster than using the standard program command sequence. the unlock bypass command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock bypass command, 20h. the device then enters the unlock bypass mode. a two-cycle unlock bypass program command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass program command, a0h; the second cycle contains the program address and data. additional data is programmed in the same manner. this mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total program - ming time. tables 10 ? 11 show the requirements for the command sequence. during the unlock bypass mode, only the unlock bypass program and unlock by - pass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. the first cycle must contain the data 90h; the second cycle the data 00h. addresses are don?t care for both cycles. the device then returns to reading array data. figure 4 illustrates the algorithm for the program operation. see the erase/pro - gram operations table in ?ac characteristics? for parameters, and to figure 17 for timing diagrams.
26 s29al016m s29al016m_00a5 august 18, 2004 notes: see tables 10 and 11 for program command sequence. figure 4. program operation chip erase command sequence chip erase is a six bus cycle operation. the chip erase command sequence is ini - tiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algorithm auto - matically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is no t required to provide any controls or tim - ings during these operations. tables 10 ? 11 show the address and data requirements for the chip erase command sequence. note that the secsi sector, autoselect, and cfi functions are unavailable when an erase operation is in progress. any commands written to the chip during the embedded erase algorithm are ig - nored. note that a hardware reset during the chip erase operation immediately terminates the operation. the chip erase command sequence should be reiniti - ated once the device has returned to reading array data, to ensure data integrity. the system can determine the status of the erase operation by using dq7, dq6, dq2, or ry/by#. see ?autoselect command sequence? for information on these status bits. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress
august 18, 2004 s29al016m_00a5 s29al016m 27 figure 5 illustrates the algorithm for the erase operation. see the erase/program operations tables in ?ac characteristics? for parameters, and to figure 18 for tim - ing diagrams. sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two addi - tional unlock write cycles are then followe d by the address of the sector to be erased, and the sector erase command. tables 10 ? 11 show the address and data requirements for the sector erase command sequence. note that the secsi sec - tor, autoselect, and cfi functions are unavailable when an erase operation is in progress. the device does not require the system to preprogram the memory prior to erase. the embedded erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. after the command sequence is written, a sector erase time-out of 50 s begins. during the time-out period, additional sector addresses and sector erase com - mands may be written. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. the time between these additional cycles must be less than 50 s, otherwise the last address and command might not be accepted, and erasure may begin. it is rec - ommended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. if the time between additional sector erase commands can be assumed to be less than 50 s, the system need not monitor dq3. any command other than sector erase or erase suspend during the time-out period resets the device to reading array data. the system must rewrite the command sequence and any additional sector addresses and commands. the system can monitor dq3 to determine if the sector erase timer has timed out. (see the ?dq3: sector erase timer? section.) the time-out begins from the rising edge of the final we# pulse in the command sequence. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. note that a hardware reset during the sector erase operation immediately terminates the operation. the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the system can determine the status of the erase operation by using dq7, dq6, dq2, or ry/by#. (refer to ?write operation status? for information on these status bits.) figure 5 illustrates the algorithm for the erase operation. refer to the erase/pro - gram operations tables in the ?ac characteristics? section for parameters, and to figure 18 for timing diagrams. erase suspend/erase resume commands the erase suspend command allows the sy stem to interrupt a sector erase oper - ation and then read data from, or program data to, any sector not selected for erasure. this command is valid only duri ng the sector erase operation, including the 50 s time-out period during the sector erase command sequence. the erase
28 s29al016m s29al016m_00a5 august 18, 2004 suspend command is ignored if written during the chip erase operation or em - bedded program algorithm. writing the erase suspend command during the sector erase time-out immediately terminates the time-out period and suspends the erase operation. addresses are ?don?t-cares? when writing the erase suspend command. when the erase suspend command is written during a sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. however, when the erase suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. after the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (the device ?erase suspends? all sectors selected for erasure.) normal read and write timings and command definitions apply. reading at any address within erase-suspended sec - tors produces status data on dq7?dq0 . the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. see ?write operation status? for information on these status bits. after an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program operation. see ?write operation status? for more information. the system may also write the autosele ct command sequence when the device is in the erase suspend mode. the device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. when the device exits the autoselect mode, the device reverts to the erase suspend mode, and is ready for another valid operation. see ?autoselect com - mand sequence? for more information. the system must write the erase resume command (address bits are ?don?t care?) to exit the erase suspend mode and continue the sector erase operation. further writes of the resume command are ignored. another erase suspend command can be written after the device has resumed erasing. note: during an erase operation, this flash device performs multiple internal op - erations that are invisible to the system. when an erase operation is suspended, any of the internal operations that were not fully completed must be restarted. as such, if this flash device is continually issued suspend/resume commands in rapid succession, erase progress will be impeded as a function of the number of suspends. the result will be a longer cu mulative erase time than without sus - pends. note that the additional suspends do not affect device reliability or future performance. in most systems rapid erase/suspend activity occurs only briefly. in such cases, erase performance will not be significantly impacted.
august 18, 2004 s29al016m_00a5 s29al016m 29 notes: 1. see tables 10 ? 11 for erase command sequence. 2. see ?dq3: sector erase timer? for more information. figure 5. erase operation program suspend/program resume command sequence the program suspend command allows th e system to interrupt a programming operation so that data can be read from any non-suspended sector. when the program suspend command is written during a programming process, the de - vice halts the program operation within 15 s maximum (5 s typical) and updates the status bits. addresses are not required when writing the program suspend command. after the programming operation has been suspended, the system can read array data from any non-suspended sector. the program suspend command may also be issued during a programming operation while an erase is sus - pended. in this case, data may be read from any addresses not in erase suspend or program suspend. if a read is needed from the secsi sector area (one-time program area), then user must use the proper command sequences to enter and exit this region. the system may also write the autosele ct command sequence when the device is in the program suspend mode. the system can read as many autoselect codes as required. when the device exits the autoselect mode, the device re - verts to the program suspend mode, and is ready for another valid operation. see autoselect command sequence for more information. after the program resume command is written, the device reverts to program - ming. the system can determine the status of the program operation using the start write erase command sequence data poll from system data = ffh? no yes erasure completed embedded erase algorithm in progress
30 s29al016m s29al016m_00a5 august 18, 2004 dq7 or dq6 status bits, just as in the standard program operation. see write operation status for more information. the system must write the program resume command (address bits are don?t care) to exit the program suspend mode and continue the programming opera - tion. further writes of the resume command are ignored. another program suspend command can be written after the device has resume programming. figure 6. program suspend/program resume program operation sequence in progress write program suspend command sequence command is also valid for erase-suspended-program operations autoselect and secsi sector read operations are also allowed data cannot be read from erase- o r program-suspended sectors write program resume command sequence read data as required done reading? no yes write address/data xxxh/30h device reverts to operation prior to program suspend write address/data xxxh/b0h wait 15 ms
august 18, 2004 s29al016m_00a5 s29al016m 31 command definitions tables ta b l e 1 0 . command definitions (x16 mode, byte# = v ih ) legend: x = don?t care ra = read address of memory location to be read. rd = read data read from location ra during read operation. pa = program address. addresses latch on falling edge of we# or ce# pulse, whichever happens later. pd = program data for location pa. data latches on risi ng edge of we# or ce# pulse, whichever happens first. sa = sector address of sector to be verified (in autoselect mode) or erased. address bits a19?a15 uniquely select any sector. command sequence (note 1) cycles bus cycles (notes 2 ? 5 ) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (note 5) 1 ra rd reset (note 6) 1 xxx f0 autoselect (note 7) manufacturer id 4 555 aa 2aa 55 555 90 x00 0001 device id, top boot (note 8) 6 555 aa 2aa 55 555 90 x01 22c4 device id, bottom boot (note 8) 6 555 aa 2aa 55 555 90 x01 2249 secsi ? sector factory protect 4 555 aa 2aa 55 555 90 x41 (note 9) sector group protect verify (note 9) 4 555 aa 2aa 55 555 90 (sa)x02 00/01 enter secsi sector region 3 555 aa 2aa 55 555 88 exit secsi sector region 4 555 aa 2aa 55 555 90 xxx 00 program 4 555 aa 2aa 55 555 a0 pa pd unlock bypass 3 555 aa 2aa 55 555 20 unlock bypass program (note 10) 2 xxx a0 pa pd unlock bypass reset (note 11) 2 xxx 90 xxx 00 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 program/erase suspend (note 12) 1 xxx b0 program/erase resume (note 13) 1 xxx 30 cfi query (note 14) 1 55 98 notes: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. shaded cells indicate read cycles. all others are write cycles. 4. during unlock and command cycles, when lower address bits are 555 or 2aa as shown in table, address bits above a11 and data bits above dq7 are don?t care. 5. no unlock or command cycles required when device is in read mode. 6. reset command is required to return to read mode (or to erase-suspend-read mode if previously in erase suspend) when device is in autoselect mode, or if dq5 goes high while device is providing status information. 7. fourth cycle of the autoselect command sequence is a read cycle. data bits dq15?dq8 are don?t care. see autoselect command sequence section for more information. 8. device id must be read in three cycles. 9. data is 00h for an unprotected sector group and 01h for a protected sector group. 10. unlock bypass command is required prior to unlock bypass program command. 11. unlock bypass reset command is required to return to read mode when device is in unlock bypass mode. 12. system may read and program in non-erasing sectors, or enter autoselect mode, when in erase suspend mode. erase suspend command is valid only during a sector erase operation. 13. erase resume command is valid only during erase suspend mode. 14. command is valid when device is ready to read array data or when device is in autoselect mode.
32 s29al016m s29al016m_00a5 august 18, 2004 ta b l e 1 1 . command definitions (x8 mode, byte# = v il ) legend: x = don?t care ra = read address of memory location to be read. rd = read data read from location ra during read operation. pa = program address. addresses latch on falling edge of we# or ce# pulse, whichever happens later. pd = program data for location pa. data latches on risi ng edge of we# or ce# pulse, whichever happens first. sa = sector address of sector to be verified (in autoselect mode) or erased. address bits a19?a15 uniquely select any sector. command sequence (note 1) cycles bus cycles (notes 2 ? 5 ) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (note 5) 1 ra rd reset (note 6) 1 xxx f0 autoselect (note 7) manufacturer id 4 aaa aa 555 55 aaa 90 x00 01 device id, top boot (note 8) 6 aaa aa 555 55 aaa 90 x02 c4 device id, bottom boot (note 8) 6 aaa aa 555 55 aaa 90 x02 49 secsi ? sector factory protect 4 aaa aa 555 55 aaa 90 x44 (note 9) sector group protect verify (note 9) 4 aaa aa 555 55 aaa 90 (sa)x04 00/01 enter secsi sector region 3 aaa aa 555 55 aaa 88 exit secsi sector region 4 aaa aa 555 55 aaa 90 xxx 00 program 4 aaa aa 555 55 aaa a0 pa pd unlock bypass 3 aaa aa 555 55 aaa 20 unlock bypass program (note 10) 2 xxx a0 pa pd unlock bypass reset (note 11) 2 xxx 90 xxx 00 chip erase 6 aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 sector erase 6 aaa aa 555 55 aaa 80 aaa aa 555 55 sa 30 program/erase suspend (note 12) 1 xxx b0 program/erase resume (note 13) 1 xxx 30 cfi query (note 14) 1 aa 98 notes: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. shaded cells indicate read cycles. all others are write cycles. 4. during unlock and command cycles, when lower address bits are 555 or aaa as shown in table, address bits above a11 are don?t care. 5. no unlock or command cycles required when device is in read mode. 6. reset command is required to return to read mode (or to erase-suspend-read mode if previously in erase suspend) when device is in autoselect mode, or if dq5 goes high while device is providing status information. 7. fourth cycle of autoselect command sequence is a read cycle. data bits dq15?dq8 are don?t care. see autoselect command sequence section or more information. 8. device id must be read in three cycles. 9. data is 00h for an unprotected sector group and 01h for a protected sector group. 10. unlock bypass command is required prior to unlock bypass program command. 11. unlock bypass reset command is required to return to read mode when device is in unlock bypass mode. 12. system may read and program in non-erasing sectors, or enter autoselect mode, when in erase suspend mode. erase suspend command is valid only during a sector erase operation. 13. erase resume command is valid only during erase suspend mode. 14. command is valid when device is ready to read array data or when device is in autoselect mode.
august 18, 2004 s29al016m_00a5 s29al016m 33 write operation status the device provides several bits to determine the status of a write operation: dq2, dq3, dq5, dq6, dq7, and ry/by#. table 12 and the following subsections describe the functions of these bits. dq7, ry/by#, and dq6 each offer a method for determining whether a program or erase operation is complete or in progress. these three bits are discussed first. dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded algorithm is in progress or completed, or whether the device is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the program or erase command sequence. during the embedded program algorithm, the device outputs on dq7 the com - plement of the datum programmed to dq7. this dq7 status also applies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a pro - gram address falls within a protected sector, data# polling on dq7 is active for approximately 1 s, then the device returns to reading array data. during the embedded erase algorithm, data# polling produces a ?0? on dq7. when the embedded erase algorithm is co mplete, or if the device enters the erase suspend mode, data# polling produces a ?1? on dq7. this is analogous to the complement/true datum output described for the embedded program algo - rithm: the erase function changes all the bits in a sector to ?1?; prior to this, the device outputs the ?complement,? or ?0.? the system must provide an address within any of the sectors selected for erasure to read valid status information on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data# polling on dq7 is active for approximately 100 s, then the device returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the se - lected sectors that are protected. when the system detects dq7 has changed from the complement to true data, it can read valid data at dq7?dq0 on the following read cycles. this is because dq7 may change asynchronously with dq0?dq6 while output enable (oe#) is asserted low. figure 19 , data# polling timings (during embedded algorithms), in the ?ac characteristics? section illustrates this. ta b l e 12 shows the outputs for data# polling on dq7. figure 7 shows the data# polling algorithm.
34 s29al016m s29al016m_00a5 august 18, 2004 notes: 1. va = valid address for programming. duri ng a sector erase operation, a valid address is an address within any sector se lected for erasure. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = ?1? because dq7 may change simulta - neously with dq5. figure 7. data# polling algorithm ry / b y # : r e a d y / b u s y# the ry/by# is a dedicated, open-drain output pin that indicates whether an em - bedded algorithm is in progress or complete. the ry/by# status is valid after the rising edge of the final we# pulse in the command sequence. since ry/by# is an open-drain output, several ry/by# pins can be tied together in parallel with a pull-up resistor to v cc . dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7?dq0 addr = va read dq7?dq0 addr = va dq7 = data? start
august 18, 2004 s29al016m_00a5 s29al016m 35 if the output is low (busy), the device is actively erasing or programming. (this includes programming in the erase suspend mode.) if the output is high (ready), the device is ready to read array data (including during the erase suspend mode), or is in the standby mode. ta b l e 12 shows the outputs for ry/by#. figures 13 , 14 , 17 and 18 show ry/by# for read, reset, program, and erase operations, respectively. dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm operation, successive read cy - cles to any address cause dq6 to toggle. (the system may use either oe# or ce# to control the read cycles.) when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for approximately 100 s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algo - rithm erases the unprotected sectors, and ignores the selected sectors that are protected. the system can use dq6 and dq2 together to determine whether a sector is ac - tively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device en - ters the erase suspend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alter - natively, the system can use dq7 (see the subsection on ?dq7: data# polling? ). if a program address falls within a pr otected sector, dq6 toggles for approxi - mately 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded program algorithm is complete. ta b l e 12 shows the outputs for toggle bit i on dq6. figure 8 shows the toggle bit algorithm in flowchart form, and the section ?reading toggle bits dq6/dq2? ex - plains the algorithm. figure 20 in the ?ac characteristics? section shows the toggle bit timing diagrams. figure 21 shows the differences between dq2 and dq6 in graphical form. see also the subsection on ?dq2: toggle bit ii? . dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (the system may use either oe# or ce# to control the read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase-suspended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are re quired for sector and mode information. refer to table 12 to compare outputs for dq2 and dq6.
36 s29al016m s29al016m_00a5 august 18, 2004 figure 8 shows the toggle bit algorithm in flowchart form, and the section ?read - ing toggle bits dq6/dq2? explains the algorithm. see also the dq6: toggle bit i subsection. figure 20 shows the toggle bit timing diagram. figure 21 shows the differences between dq2 and dq6 in graphical form. reading toggle bits dq6/dq2 refer to figure 8 for the following discussion. wh enever the system initially be - gins reading toggle bit status, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase op - eration. the system can read array data on dq7?dq0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has suc - cessfully completed the program or erase operation. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system in itially determines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as de - scribed in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algo - rithm when it returns to determine the status of the operation (top of figure 8 ).
august 18, 2004 s29al016m_00a5 s29al016m 37 figure 8. toggle bit algorithm notes: 1. read toggle bit twice to determine whether or not it is toggling. see text. 2. recheck toggle bit because it may stop toggling as dq5 changes to ?1?. see text. dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified inter - nal pulse count limit. under these conditions dq5 produces a ?1.? this is a failure condition that indicates the program or erase cycle was not successfully completed. the dq5 failure condition may appear if the system tries to program a ?1? to a location that is previously programmed to ?0.? only an erase operation can start no yes yes dq5 = 1? no yes toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete read dq7?dq0 toggle bit = toggle? read dq7?dq0 twice read dq7?dq0 (note 1) (notes 1, 2)
38 s29al016m s29al016m_00a5 august 18, 2004 change a ?0? back to a ?1.? under this condition, the device halts the opera - tion, and when the operation has exceeded the timing limits, dq5 produces a ?1.? under both these conditions, the system must issue the reset command to return the device to reading array data. dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to de - termine whether or not an erase operatio n has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase com - mand. when the time-out is complete, dq3 switches from ?0? to ?1.? the system may ignore dq3 if the system can guarantee that the time between additional sector erase commands will always be less than 50 s. see also the ?sector erase command sequence? section. after the sector erase command sequence is written, the system should read the status on dq7 (data# polling) or dq6 (toggle bit i) to ensure the device has ac - cepted the command sequence, and then read dq3. if dq3 is ?1?, the internally controlled erase cycle has begun; all further commands (other than erase sus - pend) are ignored until the erase operation is complete. if dq3 is ?0?, the device will accept additional sector erase commands. to ensure the command has been accepted, the system software should check the status of dq3 prior to and fol - lowing each subsequent sector erase command. if dq3 is high on the second status check, the last command might not have been accepted. table 12 shows the outputs for dq3. ta b l e 1 2 . write operation status notes: 1. dq5 switches to ?1? when an embedded program or embedded erase operation has exceeded the maximum timing limits. see ?dq5: exceeded timing limits? for more information. 2. dq7 and dq2 require a valid address when reading status in formation. refer to the appropriate subsection for further details. operation dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) ry/by# standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 embedded erase algorithm 0 toggle 0 1 toggle 0 program suspend mode program- suspend read program- suspended sector invalid (not allowed) 1 non-program suspended sector data 1 erase suspend mode reading within erase suspended sector 1 no toggle 0 n/a toggle 1 reading within non-erase suspended sector data data data data data 1 erase-suspend-program dq7# toggle 0 n/a n/a 0
august 18, 2004 s29al016m_00a5 s29al016m 39 absolute maximum ratings storage temperature, plastic packages . . . . . . . . . . . . . . . . .?65 c to +150 c ambient temperature with power applied . . . . . . . . . . . . . . .?65 c to +125 c voltage with respect to ground v cc (note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .?0.5 v to +4.0 v a9 , oe# , and reset# (note 2) . . . . . . . . . . . . . . . . ?0.5 v to +12.5 v all other pins (note 1) . . . . . . . . . . . . . . . . . . . . . ?0.5 v to v cc +0.5 v output short circuit current (note 3). . . . . . . . . . . . . . . . . . . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is ?0.5 v. during voltage transitions, input or i/o pins may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 9 . maximum dc voltage on input or i/o pins is v cc +0.5 v. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods up to 20 ns. see figure 10 . 2. minimum dc input voltage on pins a9, oe#, and reset# is -0.5 v. during voltage transitions, a9, oe#, and reset# may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 9 . maximum dc input voltage on pin a9 is +12.5 v which may overshoot to 14.0 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rating con - ditions for extended periods may affect device reliability. operating ranges industrial (i) devices ambient temperature (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . ?40c to +85c v cc supply voltages v cc for full voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 v to 3.6 v v cc for regulated range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 v to 3.6 v operating ranges define those limits between which the functionality of the device is guaranteed. figure 9. maximum negative overshoot waveform figure 10. maximum positive overshoot waveform 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v
40 s29al016m s29al016m_00a5 august 18, 2004 dc characteristics cmos compatible notes: 1. the i cc current listed is typically less than 2 ma/mhz, with oe# at v ih . typical v cc is 3.0 v. 2. maximum i cc specifications are tested with v cc = v cc max. 3. i cc active while embedded erase or embedded program is in progress. 4. at extended temperature range (>+85 c), typical current is 5 a and maximum current is 10 a. 5. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 30 ns. 6. not 100% tested. 7. v cc voltage requirements. parameter description test conditions min typ max unit i li input load current v in = v ss to v cc , v cc = v cc max 1.0 a i lit a9 input load current v cc = v cc max ; a9 = 12.5 v 35 a i lr reset leakage current v cc = v cc max ; reset# = 12.5 v 35 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 a ce# = v il, oe# = v ih, byte mode 10 mhz 35 50 ma i cc1 v cc active read current (notes 1, 2) 5 mhz 15 20 1 mhz 2.5 10 ce# = v il, oe# = v ih, word mode 10 mhz 35 50 5 mhz 15 20 1 mhz 2.5 10 i cc2 v cc active write current (notes 2, 3, 5) ce# = v il, oe# = v ih 40 60 ma i cc3 v cc standby current (notes 2, 4) ce#, reset# = v cc 0.3 v 0.4 5 a i cc4 v cc standby current during reset (notes 2, 4) reset# = v ss 0.3 v 0.8 5 a i cc5 automatic sleep mode (notes 2, 4, 6) v ih = v cc 0.3 v; -0.1 < v il 0.3 v 0.4 5 a v il input low voltage (notes 6, 7) -0.5 0.6 v v ih input high voltage (notes 6, 7) 0.7 v cc v cc + 0.5 v v id voltage for autoselect and temporary sector unprotect v cc = 3.3 v 11.5 12.5 v v ol output low voltage i ol = 4.0 ma, v cc = v cc min 0.45 v v oh1 output high voltage i oh = -2.0 ma, v cc = v cc min 0.85 x v cc v v oh2 i oh = -100 a, v cc = v cc min v cc ?0.4 v lko low v cc lock-out voltage (note 4) 2.3 2.5 v
august 18, 2004 s29al016m_00a5 s29al016m 41 test conditions key to switching waveforms figure 12. input waveforms and measurement levels note: diodes are in3064 or equivalent figure 11. test setup table 13. test specifications 2.7 k ? c l 6.2 k ? 3.3 v device under te s t test condition 90, 100 unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times 5 ns input pulse levels 0.0 or v cc v input timing measurement reference levels 0.5 v cc v output timing measurement reference levels 0.5 v cc v waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) v cc 0.0 v 0.5 v cc output measurement level input 0.5 v cc
42 s29al016m s29al016m_00a5 august 18, 2004 ac characteristics read operations notes: 1. not 100% tested. 2. see figure 11 and table 13 for test specifications. figure 13. read operations timings parameter description speed options jedec std test setup 90 100 unit t avav t rc read cycle time (note 1) min 90 100 ns t avqv t acc address to output delay ce# = v il oe# = v il max 90 100 ns t elqv t ce chip enable to output delay oe# = v il max 90 100 ns t glqv t oe output enable to output delay max 25 ns t ehqz t df chip enable to output high z (note 1) max 20 ns t ghqz t df output enable to output high z (note 1) max 20 ns t oeh output enable hold time (note 1) read min 0 ns to g g l e a n d data# polling min 10 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first (note 1) min 0 ns t ce outputs we# addresses ce# oe# high z output valid high z addresses stable t rc t acc t oeh t oe 0 v ry/by# reset# t df t oh
august 18, 2004 s29al016m_00a5 s29al016m 43 ac characteristics hardware reset (reset#) note: not 100% tested. figure 14. reset# timings parameter description all speed options jedec std test setup unit t ready reset# pin low (during embedded algorithms) to read or write (see note) max 20 s t ready reset# pin low (not during embedded algorithms) to read or write (see note) max 500 ns t rp reset# pulse width min 500 ns t rh reset# high time before read (see note) min 50 ns t rpd reset# low to standby mode min 20 s t rb ry/by# recovery time min 0 ns reset# ry/by# ry/by# t rp t ready reset timings not during embedded algorithms t ready ce#, oe# t rh ce#, oe# reset timings during embedded algorithms reset# t rp t rb
44 s29al016m s29al016m_00a5 august 18, 2004 ac characteristics erase/program operations notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. 3. if a program suspend command is issued within t poll , the device requires t poll before reading status data, once programming has resumed (that is, the program resume command has been written). if the suspend command was issued after t poll , status data is available immediately after programming has resumed. see figure 15 . parameter speed options jedec std description 90 100 unit t avav t wc write cycle time (note 1) min 90 100 ns t avwl t as address setup time min 0 ns t wlax t ah address hold time min 45 ns t dvwh t ds data setup time min 35 ns t whdx t dh data hold time min 0 ns t oes output enable setup time min 0 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 35 ns t whwl t wph write pulse width high min 30 ns t whwh1 t whwh1 programming operation (note 2) typ 18 s t whwh2 t whwh2 sector erase operation (note 2) typ 1 sec t vcs v cc setup time (note 1) min 50 s t rb recovery time from ry/by# min 0 ns t busy program/erase valid to ry/by# delay max 90 100 ns t poll program valid before status polling (note 3 ) max 4 s
august 18, 2004 s29al016m_00a5 s29al016m 45 ac characteristics notes: 1. pa = program address, pd = program data, d out is the true data at the program address. 2. illustration shows device in word mode. figure 15. program operation timings oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t cs status d out program command sequence (last two cycles) ry/by# t rb t busy t ch pa t poll
46 s29al016m s29al016m_00a5 august 18, 2004 ac characteristics notes: 1. sa = sector address (for sector erase), va = valid address for reading status data (see ?write operation status?). 2. illustration shows device in word mode. figure 16. chip/sector erase operation timings oe# ce# addresses v cc we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch in progress complete t whwh2 va va erase command sequence (last two cycles) read status data ry/by# t rb t busy
august 18, 2004 s29al016m_00a5 s29al016m 47 ac characteristics note: va = valid address. illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. figure 17. data# polling timings (during embedded algorithms) note: va = valid address; not required for dq6. illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. figure 18. to g g l e b i t t i m i n g s (during embedded algorithms) we# ce# oe# high z t oe high z dq7 dq0?dq6 ry/by# t busy complement true addresses va t oeh t ce t ch t oh t df va va status data complement status data true valid data valid data t acc t poll t rc we# ce# oe# high z t oe dq6/dq2 ry/by# t busy a ddresses va t oeh t ce t ch t oh t df va va t acc t rc valid data valid status valid status (first read) (second read) (stops toggling) valid status va
48 s29al016m s29al016m_00a5 august 18, 2004 ac characteristics note: the system may use ce# or oe# to toggle dq2 and dq6. dq2 toggles only when read at an address within an erase-suspended sector. figure 19. dq2 vs. dq6 for erase and erase suspend operations temporary sector unprotect note: not 100% tested. figure 20. temporary sector unprotect/timing diagram parameter all speed options jedec std description unit t vidr v id rise and fall time (see note) min 500 ns t rsp reset# setup time for temporary sector unprotect min 4 s enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing reset# t vidr 12 v 0 or 3 v ce# we# ry/by# t vidr t rsp program or erase command sequence
august 18, 2004 s29al016m_00a5 s29al016m 49 ac characteristics note: for sector protect, a6 = 0, a1 = 1, a0 = 0. for sector unprotect, a6 = 1, a1 = 1, a0 = 0. figure 21. sector protect/unprotect timing diagram sector protect: 150 s sector unprot ect: 15 ms 1 s reset# sa, a6, a1, a0 data ce# we# oe# 60h 60h 40h valid* valid* valid* status sector protect/unprotect verify v id v ih
50 s29al016m s29al016m_00a5 august 18, 2004 ac characteristics alternate ce# controlled erase/program operations notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. 3. if a program suspend command is issued within t poll , the device requires t poll before reading status data, once programming has resumed (that is, the program resume command has been written). if the suspend command was issued after t poll , status data is available immediately after programming has resumed. see figure 22 . parameter speed options jedec std description 90 100 unit t avav t wc write cycle time (note 1) min 90 100 ns t avel t as address setup time min 0 ns t elax t ah address hold time min 45 ns t dveh t ds data setup time min 35 ns t ehdx t dh data hold time min 0 ns t oes output enable setup time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 35 ns t ehel t cph ce# pulse width high min 25 ns t whwh1 t whwh1 programming operation (note 2) typ 18 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.7 sec t rh reset# high time before write min 50 ns t poll program valid before status polling (note 3) max 4 s
august 18, 2004 s29al016m_00a5 s29al016m 51 ac characteristics notes: 1. pa = program address, pd = program data, dq7# = complement of the data written to the device, d out = data written to the device. 2. figure indicates the last two bus cycles of the command sequence. 3. word mode address used as an example. figure 22. alternate ce# controlled write operation timings t ghel t ws oe# ce# we# reset# t ds data t ah addresses t dh t cp dq7#, d out t wc t as t cph pa data# polling a0 for program 55 for erase t rh t whwh1 or 2 ry/by# t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase t busy dq15 t poll
52 s29al016m s29al016m_00a5 august 18, 2004 erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25 c, v cc = 3.0 v, 10,000 cycles, checkerboard data pattern. 2. under worst case conditions of 90c, v cc = 2.7 v, 100,000 cycles. 3. the typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. in the pre-programming step of the embedded erase algorithm, all bytes are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. see tables 2 ? 3 for further information on command definitions. tsop pin and bga package capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. parameter typ (note 1) max (note 2) unit comments sector erase time 0.7 7.5 s excludes 00h programming prior to erasure (note 4) chip erase time 32 s byte programming time 18 s word programming time 18 s excludes system level overhead (note 5) chip programming time (note 3) byte mode 36 s word mode 19 s parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 tsop 6 7.5 pf bga 4.2 5.0 pf c out output capacitance v out = 0 tsop 8.5 12 pf bga 5.4 6.5 pf c in2 control pin capacitance v in = 0 tsop 7.5 9 pf bga 3.9 4.7 pf
august 18, 2004 s29al016m_00a5 s29al016m 53 physical dimensions ts 048?48-pin standard tsop note: bsc is an ansi standard for basic space centering. dwg rev aa; 10/99
54 s29al016m s29al016m_00a5 august 18, 2004 physical dimensions tsr048?48-pin reverse tsop note: bsc is an ansi standard for basic space centering. dwg rev aa; 10/99
august 18, 2004 s29al016m_00a5 s29al016m 55 physical dimensions fba048?48-ball fine-pitch ball grid array (bga) 6 x 8 mm package note: bsc is an ansi standard for basic space centering. dwg rev af; 10/99
56 s29al016m s29al016m_00a5 august 18, 2004 physical dimensions laa064?64-ball fortified ball grid array (bga) 13 x 11 mm package note: bsc is an ansi standard for basic space centering.
august 18, 2004 s29al016m_00a5 s29al016m 57 revision summary revision a (january 30, 2004) initial release. revision a + 1 (february 20, 2004) product selector guide removed regulated voltage range for the speed option. ordering information included explanations of the package markings for tsop and bga packages. word/byte program sequence added guidance for programming the same address multiple times without inter - vening erases. operating ranges removed reference to regulated voltage ranges. ac characteristics (read options table) the timing specifications for t ehqz and t ghqz were tightened to 20 ns. erase and programming performance table added the byte programming time specification. revision a + 2 (february 25, 2004) product selector guide added tray and 13? tape and reel to the packing type. removed ?2? from end of package marking. revision a + 3 (march 24, 2004) table 7, ?system interface string? changed description to rfu for 23h word/46h byte mode. added additional information to description for 24h word/28h byte mode. removed references to v cc in note. cmos compatible updated the min and max for v il and the min for v ih. corrected test conditions for i cc5. figure 12, ?input waveforms and measurement levels? added v cc to figure. byte# timings for read operations and byte# timings for write operations removed figures. erase/program operations updated t busy 100 ns speed option to have 100 ns min. alternate ce# controlled erase/program operations added t rh parameter to table. connection diagrams deleted the reverse tsop diagram.
58 s29al016m s29al016m_00a5 august 18, 2004 revision a + 4 (april 19, 2004) product selector guide added regulated voltage range for the speed option. operating ranges added regulated voltage ranges. erase/program operations table changed t busy from min to max. erase and programming performance table added cycling conditions to note 1 and note 2. revision a + 5 (august 18, 2004) valid combinations table updated entire table. secsi sector addressing table updated the x8 address ranges. colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contem plated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and c ould lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerabl e (i.e., submersible repeater and artificial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages ari sing in connection with above-men - tioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, dam age or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain re strictions on export under the foreign exchange and foreign trade law of japan, the us export administration regulations or the applicable laws of any oth er country, the prior au - thorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subject to change without notice.this document may contain information on a spansion product under development by spansion llc. spansion llc reserves the right to change or disc ontinue work on any product without notice. the information in t his document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. spansion llc assumes no liability for any damages of any kind arising out of the use of the information in this document. copyright ? 2004 spansion llc. all rights reserved. spansion, the spansion logo, mirrorbit, combinations thereof, and expressfl ash are trademarks of span - sion llc. other company and product names used in this publication are for identification purposes only and may be trademarks o f their respective compa - nies.

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